The present invention relates to a driving apparatus for a commutatorless DC motor.
The Japanese Patent Publication No. 61-3193 (the Japanese Patent Application No. 50-87617) discloses a commutatorless DC motor having an armature winding with a fixed three-phase Y connection, a permanent magnet rotor, semiconductor switching unit for controlling a commutation of an armature current of the armature winding, and a pulse generating circuit for on-off controlling the semiconductor switching unit based on induced voltages which are generated at each phase of the armature winding. The semiconductor switching unit is composed of six switching transistors connected by a three-phase bridge connection. The six switching transistors are on-off controlled by the pulse generating circuit, and they switch the armature current flowing through the armature winding. The pulse generating circuit has a circuit for forming a pulse signal which represents a zero-cross point of the induced voltages by means of pulse shaping and logically calculating the induced voltages of the armature winding, a PLL (Phase Locked Loop) circuit for inputting the pulse signal which represents the zero-cross point of induced voltages, and a circuit for forming six drive pulse signals for controlling the semiconductor switching unit based on an output from the PLL circuit. The PLL circuit has a voltage-controlled oscillator, a 1/2 frequency divider for 1/2 frequency dividing an output of the voltage-controlled oscillator, a phase comparator for inputting an output of the 1/2 frequency divider and the pulse signal representing the zero-cross point of induced voltages, and a low-pass filter for feeding back an output of the phase comparator to the voltage-controlled oscillator. The PLL circuit detects a phase difference between the output of the 1/2 frequency divider and the pulse signal representing the zero-cross point of induced voltages, feeds it back to the voltage-controlled oscillator through the low-pass filter, and gives a pulse output signal which has a 90.degree. phase difference in relation to the pulse signal representing the zero-cross point of induced voltages.
The pulse generating circuit forms three drive pulses out of six drive pulses by means of 1/3 frequency dividing the pulse output signal of the PLL circuit and, forms the remaining three drive pulses by means of 1/3 frequency dividing the pulse output signal of the PLL circuit after inverting its phase. Using these six pulse signals, the pulse generating circuit on-off controls each of the six switching transistors of the semiconductor switching unit.
According to the commutatorless DC motor with the above-mentioned arrangement, since the phase difference between the pulse output signal of the PLL circuit and the pulse signal representing the zero-cross point of induced voltages is detected and the phase difference is fed back to the voltage-controlled oscillator through the low-pass filter, a commutation timing of the armature current is adjusted only by the result of integrating the phase difference. Thereby, in cases where the phase difference is large such as a shift to running based on the induced voltages from synchronized operation at a starting of the motor and an overloading, a response time until the voltage-controlled oscillator follows the output of the phase comparator is extended, and in certain cases the voltage-controlled oscillator can not follow, causing the motor step-out. Moreover, according to the commutatorless DC motor with the above-mentioned arrangement, since the pulse output signal of the PLL circuit and the pulse signal representing the zero-cross point of induced voltages are controlled so that the phase difference is always 90.degree., it is not easily possible to change the commutation timing. If the commutation timing can easily be changed, it is possible to selectively change the commutation timing corresponding to variations in revolution and the load of the motor, whereby the commutatorless DC motor can be driven more stably.
Furthermore, in the commutatorless DC motor, spike voltages are generated in the armature winding when commutating the armature current, that is, when switching the armature current. The spike voltages are superposed on the induced voltages of each phase of the armature winding. The spike voltages remain after the induced voltages are pulse shaped and cause an adverse effect on the detection of the zero-cross point of induced voltages. In the Japanese Patent Publication No. 58-25038 (the Japanese Patent Application No. 50-105932), the induced voltages superposed with spike voltages are each integrated in the integration circuit, the integrated outputs are each compared with a ground voltage and pulse shaped, and six drive pulse signals for controlling a commutation are formed from the pulse-shaped integrated outputs through a logic circuit. Thereby, since both the induced voltages and spike voltages are integrated together, an error is generated in the position of the zero-cross point of induced voltages. Hence, there is a problem that the motor's stable driving is impeded.